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RFF70N06
Data Sheet March 1999 File Number
4073.2
25A, 60V, 0.025 Ohm, N-Channel Power MOSFET
The RFF70N06 N-Channel power MOSFET is manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI circuits gives optimum utilization of silicon, resulting in outstanding performance. It was designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. These transistors can be operated directly from integrated circuits. Reliability screening is available as either commercial or TX/TXV equivalent of MIL-S-19500. Contact Intersil Corporation High-Reliability Marketing group for any desired deviations from the data sheet. Formerly developmental type TA49007.
Features
* 25A, 60V * rDS(ON) = 0.025 * Temperature Compensating PSPICETM Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * 150oC Operating Temperature * Reliability Screened Current is limited by the package capability.
Symbol
D
Ordering Information
PART NUMBER RFF70N06 PACKAGE TO-254AA BRAND RFF70N06
G
S
NOTE: When ordering, use the entire part number.
Commercial Version: RFG70N06.
Packaging
JEDEC TO-254AA
GATE SOURCE DRAIN
PACKAGE TAB (ISOLATED)
CAUTION: Berylia Warning per MIL-S-19500. Refer to package specifications.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICETM is a trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
RFF70N06
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Drain Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 4) (Figure 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Single Pulse Avalanche Rating (Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL RFF70N06 60 60 20 25 (Note 2) Refer to Peak Current Curve Refer to UIS Curve 100 0.80 -55 to 150 260 UNITS V V V A
W W/oC oC
oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 125oC. 2. Current is limited by the package capability.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V VGS = VDS, ID = 250A VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 125oC VGS = 20V, TC = 125oC ID = 25A, VGS = 10V VDD = 30V, ID 25A, RL = 1.2, VGS = 10V, RGS = 2.35 (Figures 13, 16, 17) MIN 60 2.0 VGS = 0 to 20V VGS = 0 to 10V VGS = 0 to 2V VDD = 30V, ID = 25A, RL = 1.2 IG(REF) = 1.0mA (Figures 18, 19) TYP 3.0 25 70 60 25 3100 900 300 MAX 4.5 25 250 100 0.025 240 70 170 150 65 215 260 145 7 1.25 48 UNITS V V A A ns ns ns ns ns ns nC nC nC pF pF pF
oC/W oC/W
Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance (Note 3) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 10V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(10) Qg(TH) CISS COSS CRSS RJC RJA
VDS = 25V, VGS = 0V, f = 1MHz (Figure 12)
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Diode Reverse Recovery Time NOTES: 3. Pulse test: pulse width 300ms, duty cycle 2%. 4. Repetitive rating: pulse width is limited by maximum junction temperature. See Transient Thermal Impedance curve Figure 3). SYMBOL VSD trr ISD = 25A ISD = 25A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP 1.1 190 MAX 1.5 300 UNITS V ns
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RFF70N06 Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 TC , CASE TEMPERATURE (oC) 125 150 ID , DRAIN CURRENT (A)
Unless Otherwise Specified
30 25 20 15 10
5 0 25 50 75 100 125 150 TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
2 1 THERMAL IMPEDANCE ZJC, NORMALIZED 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 10-5 SINGLE PULSE 10-4 10-3 10-2 10-1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 100 101 t, RECTANGULAR PULSE DURATION (s)
PDM
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500 TC = 25oC IDM , PEAK CURRENT (A) ID , DRAIN CURRENT (A)
103
FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT CAPABILITY AS FOLLOWS:
100 100s
150 - T C I = I 25 --------------------- 125
102
10
1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) VDSS MAX = 60V 10ms 100ms DC 100
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION VGS = 10V TC = 25oC 101 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101
1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
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RFF70N06 Typical Performance Curves
300 IAS , AVALANCHE CURRENT (A) 150 100 75 STARTING TJ = 150oC ID , DRAIN CURRENT (A) 125 100 75 50 VGS = 4.5V VGS = 5V VGS = 10V VGS = 20V VGS = 7V
Unless Otherwise Specified
(Continued)
STARTING TJ = 25oC 10
250s PULSE TEST TC = 25oC VGS = 6V
1 0.01
If R = 0 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) If R 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] 0.1 1 10 100 tAV, TIME IN AVALANCHE (ms) 1000
25 0 0
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
2 4 6 8 VDS , DRAIN TO SOURCE VOLTAGE (V)
10
FIGURE 7. SATURATION CHARACTERISTICS
IDS(ON), DRAIN TO SOURCE CURRENT (A)
150 125 100 VDD = 15V PULSE DURATION = 250s DUTY CYCLE = 0.5% MAX
25oC
NORMALIZED DRAIN TO SOURCE ON RESISTANCE
-55oC
2.5 PULSE DURATION = 250s VGS = 10V, ID = 25A
2.0
150oC 75 50 25 0 0 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V)
1.5
1.0
0.5
0 -80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
2.0
VGS = VDS, ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
2.0 ID = 250A 1.5
THRESHOLD VOLTAGE
NORMALIZED GATE
1.5
1.0
1.0
0.5
0.5
0 -80
-40
0
40
80
120
160
0 -80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
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RFF70N06 Typical Performance Curves
5000 VGS = 0V, f = 0.1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGS
Unless Otherwise Specified
(Continued)
60 VDS , DRAIN TO SOURCE VOLTAGE (V) VDD = BVDSS 45 VDD = BVDSS 7.5 10.0 VGS , GATE TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
4000
3000
30
2000
RL = 1.2 IG(REF) = 1.0mA VGS = 10V 0.75 BVDSS 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS 0.50 BVDSS 0.25 BVDSS
5.0
15
2.5
1000
0 0 5 10 15 20 25 VDS , DRAIN TO SOURCE VOLTAGE (V)
0 20
IG(REF) IG(ACT)
t, TIME (s)
80
IG(REF) IG(ACT)
0
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
tON VDS VDS VGS RL
+
tOFF td(OFF) tr tf 90%
td(ON)
90%
DUT RGS VGS
-
VDD
0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 16. SWITCHING TIME TEST CIRCUIT
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
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RFF70N06 Test Circuits and Waveforms
(Continued)
VDS RL VDD VDS VGS = 20V VGS
+
Qg(TOT)
Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Ig(REF) 0 VGS = 10V
DUT Ig(REF)
FIGURE 18. GATE CHARGE TEST CIRCUIT
FIGURE 19. GATE CHARGE WAVEFORMS
Data Packages - Intersil Power Transistors
TX and TXV Equivalents 1. TX/TXV Equivalent - Standard Data Package A. Certificate of Compliance B. Assembly Flow Chart C. Preconditioning - Attributes Data Sheet D. Group A - Attributes Data Sheet - Attributes Data Sheet 2. TX/TXV Equivalent - Optional Data Package A. Certificate of Compliance B. Assembly Flow Chart C. Preconditioning - Attributes Data Sheet - Precondition Lot Traveler - Pre and Post Burn-In Read and Record Data D. Group A - Attributes Data Sheet - Group A Lot Traveler E. Group B - Attributes Data Sheet - Group B Lot Traveler - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup B3) - Bond Strength Data (Subgroup B3) - Pre and Post High Temperature Operating Life Read and Record Data (Subgroup B6) F. Group C - Attributes Data Sheet - Group C Lot Traveler - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup C6) - Bond Strength Data (Subgroup C6) E. Group B F. Group C - Attributes Data Sheet
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RFF70N06 PSPICE Electrical Model
SUBCKT RFF70N06 2 1 3 ;
CA 12 8 5.20e-9 CB 15 14 5.20e-9 CIN 6 8 2.80e-9
10
rev 5/29/95
LDRAIN DPLCAP 5 DRAIN 2 RSCL1 RSCL2 51 + 5 ESCL 51 50 ESG + 6 8 RDRAIN 16 EVTHRESH + 19 8 6 MOS1 RIN CIN 8 RSOURCE 7 + 17 EBREAK 18 MOS2 11 DBODY DBREAK RLDRAIN
DBODY 7 5 DBDMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 68.7 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRESH 6 21 19 8 1 EZTEMPCO 20 6 18 22 1 IT 8 17 1
GATE LGATE 9 1 RLGATE
EZTEMPCO 20 + 18 22 RGATE
21
LDRAIN 2 5 1e-9 LGATE 1 9 6.04e-9 LSOURCE 3 7 2.24e-9 MOS1 16 6 8 8 MSTRONG M = 0.99 MOS2 16 21 8 8 MWEAK M = 0.01 RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 8.03e-3 RGATE 9 20 1 RIN 6 8 1e9 RLDRAIN 2 5 10 RLGATE 1 9 60.4 RLSOURCE 3 7 22.4 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 7.20e-3 RTHRESH 22 8 RTHRESMOD 1 RZTEMPCO 18 19 RZTEMPCOMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
LSOURCE 3 SOURCE RLSOURCE
S1A 12 S1B CA + EGS 6 8 13 8 14 13
S2A 15 S2B 13 CB + EDS 5 8 14 17
RBREAK 18 RZTEMPCO IT 19 VBAT + 22 RTHRESH
VBAT 22 19 DC 1 ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),3))} .MODEL DBDMOD D (IS = 1e-12 RS = 11.01e-3 TRS1 = 1.75e-3 TRS2 = -0.06e-6 CJO = 2.70e-9 TT = 7.82e-8 M = 0.45) .MODEL DBREAKMOD D (RS = 88e-3 TRS1 = 1.50e-3 TRS2 = 0) .MODEL DPLCAPMOD D (CJO = 2.60e-9 IS = 1e-30 N = 10 M=0.7) .MODEL MSTRONG NMOS (VTO = 3.85 KP = 47.2 IS = 1e-30 N = 10 TOX = 1L = 1u W = 1u) .MODEL MWEAK NMOS (VTO = 3.09 KP = 47.2 IS = 1e-30 N = 10 TOX = 1L = 1u W = 1u) .MODEL RBREAKMOD RES (TC1 = 1e-3 TC2 = 0) .MODEL RDRAINMOD RES (TC1 = 7e-3 TC2 = 1.90e-5) .MODEL RDSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RSCLMOD RES (TC1 = 0 TC2 = 0) .MODEL RTHRESHMOD RES (TC1 = -3.10e-3 TC2 = -1e-5) .MODEL RZTEMPCOMOD RES (TC1 = -2.25e-3 TC2 = -5.75e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.0 VOFF= -4.0) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.0 VOFF= -6.0) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF= 2.0) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.0 VOFF= -2.0) .ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991.
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RFF70N06 Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table)
.
Delta Tests and Limits (JANTX/JANTXV Equivalent)
PARAMETER
Gate to Source Leakage Current Zero Gate Voltage Drain Current On Resistance Gate Threshold Voltage
SYMBOL IGSS IDSS rDS(ON) VGS(TH)
TEST CONDITIONS
VGS = 20V, TC = 25oC VDS = 80% Rated Value, TC = 25oC TC = 125oC at Rated ID ID = 1.0mA, TC = 25oC
MAX 20 (Note 5) 25 (Note 5) 20% (Note 6) 20% (Note 6)
UNITS nA A V
NOTES: 5. Or 100% of Initial Reading (whichever is greater). 6. Of Initial Reading.
Screening Information
TEST
Gate Stress Pind PDA Pre Burn-In Test (Note 7) Steady State Gate Bias (Gate Stress) VGS = 30V, t = 250s Optional 10% MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC) MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours All Delta Parameters Listed in the Delta Tests and Limits Table MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 168 hours MIL-S-19500, Group A, Subgroup 2
JANTX/JANTXV EQUIVALENT
Interim Electrical Tests (Note 7) Steady State Reverse Bias (Drain Stress)
Final Electrical Tests (Note 7)
NOTE: 7. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER
Safe Operating Area Unclamped Inductive Switching Thermal Response Thermal Impedance
SYMBOL SOA IAS VSD VSD
TEST CONDITIONS
VDS = 48V, t = 10ms VGS(PEAK) = 15V, L = 0.1mH tH = 100ms; VH = 25V, IH = 4A tH = 500ms; VH = 25V, IH = 4A
MAX 4.8 75 220 330
UNITS A A mV mV
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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